RESEARCH TRIANGLE PARK, N.C. — The Semiconductor Research Corporation is teaming up with five universities to create a new research center designed to develop new semiconductor materials.

The SRC, its industry partners and the universities are pooling $7 million to fund the effort over the next three years. Research will focus on “stretching” the performance of silicon in complimentary metal oxide semiconductors, or CMOS.

Researchers are seeking to improve the performance of silicon chips with what it calls non-classical materials. These materials include chemical elements found in the third and fifth columns of chemistry periodical tables, thus the term III-V compounds, according to the SRC.

The SRC hopes that the collective research of the new lab will improve chip speeds and lower power dissipation. The organization, which is funded by private industry partners, forecasts the research could have “significant impact” on chip manufacturing as early as 2012.

Leading the lab effort will be UC-Santa Barbara. Other university members include Stanford, UC-San Diego, University of Massachusetts-Amherst and the University of Minnesota.

“We expect that a new class of compound semiconductors can provide better peak velocities and lower voltages and allow the industry to supplement silicon’s critical paths for speed and power,” said Mark Rodwell, a professor at UC-Santa Barbara who will serve as the Center’s director. “This new research effort proposes to benefit a long line of applications and users.”

Researchers are concerned about reaching the capacity of silicon under Moore’s Law, which dates to 1965. That forecast predicted a doubling of transistor capacity on silicon chips every 18 months.

“While all good things must come to an end, we plan for the Non-Classical CMOS Research Center to ensure that Moore’s Law will be alive and well for several more generations,” said Jim Hutchby, director of Device Sciences for the Global Research Collaboration, which is part of the SRC.

The group is tasked with narrowing the options for carrying CMOS to what the SRC calls the “ultimate limit”.

“And when the day comes that Moore’s Law for classical silicon CMOS is no longer a viable solution, we’ll have developed a new set of materials and devices for improvements to speed and power of the historically successful CMOS technology,” Hutchby added.

The universities were selected to participate in the lab during a competition lasting several months.

Industry partners of the SRC include Advanced Micro Devices Inc., Applied Materials Inc., Axcelis Technologies Inc., Cadence Design Systems, Freescale Semiconductor Inc., Hewlett-Packard Co., IBM Corp., Intel Corp., LSI Logic Corp., Mentor Graphics Corp., The Mitre Corp., Novellus Systems Inc., Rohm and Haas Electronic Materials, and Texas Instruments Corp.