Ziptronix, a developer of manufacturing technology for the semiconductor industry, has unveiled a 3-D integrated circuit process that it says will advance current system-on-a-chip (SoC) technology by presenting a large menu of previously impossible integration choices.
This process enables for the first time, Ziptronix says, the integration of memory and analog circuitry without the cost or scaling penalties inherent in conventional 2-D embedded technologies. The company says its 3-D IC technology will improve time-to-market by allowing late-stage integration of existing devices. Overall system performance will be improved by integrating devices on the same dimensional scale used to build them.
“3-D integration offers the Holy Grail of simultaneous improvements in size, cost, speed and power dissipation,” Doug Milner, chief executive officer of Ziptronix, said in a statement. “Previous attempts at 3-D integration have been geared towards a single device with limited material combinations. Ziptronix is the first to enable the creation of true 3-D structures with any combination of materials, and virtually no device or packaging limitations. This development advances SoC design methodology, and eliminates the compromises previously inherent to SoC technology.”
Ziptronix’ process yields a thin die with no interconnect or packaging limitations. The RTP-based company provides an integrated pair of chips to be bumped or assembled, as opposed to using bumping itself as the integration process. These benefits are the result of Ziptronix’ proprietary ZiROC bonding process and ZiCON interconnect process.
The 3-D integration process from Ziptronix is supported in standard fab ambient conditions, and requires no special equipment or materials. This technology is projected to have a significant impact on wireless applications, network processors and CPUs, the company says.
Ziptronix: www.ziptronix.com
